1. The Field of the Invention
The present invention is directed to a method for manufacturing a semiconductor substrate having thereon a multi-layer structure with a substantially completely filled trench, channel, or via using a robust, pressure aluminum fill process. More particularly, the invention relates to methods of manufacturing a semiconductor device on a semiconductor substrate having a trench, channel, or via that is coated with a barrier layer and where a metallization layer on the barrier layer substantially completely fills up the trench, channel, or via.
2. The Relevant Technology
In the context of this document, the term xe2x80x9csemiconductor substratexe2x80x9d is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term xe2x80x9csubstratexe2x80x9d refers to any supporting structure including but not limited to the semiconductor substrates described above. Used of the term xe2x80x9csemiconductor substratexe2x80x9d herein also includes structures such as silicon-on-insulator and silicon-on-sapphire.
Various interconnection layers are formed on semiconductor substrates for electrically connecting elements thereon to each other as well as to external circuits. These interconnection layers are typically formed of polysilicon films, high melting point metal films, high melting point metal silicide films, aluminum films, and aluminum alloy films. In recent years, reduction of the interconnection layer resistivity has been desirable in semiconductor integrated circuit devices which are highly integrated for high speed operation. Where aluminum interconnection structures are used, the semiconductor integrated circuit devices having aluminum interconnection structures are preferably formed of aluminum films or aluminum alloy films that have a small resistivity. Poor step coverage of an aluminum film used to fill a trench, channel, or via, and the consequent creation of a voids within the trench, channel, or via, is overcome by using a high temperature, high pressure treatment. A difficulty with this process is that the steps taken to eliminate voids in the trench, channel, or via also undermine the integrity of the barrier layer.
In integrated circuit manufacture, it is often desirable to accomplish a multi-level metallization scheme. Achieving an optimally high integrated circuit density can be accomplished by arranging conductive connections between individual electrical elements of an integrated circuit in planes lying above one another and to simultaneously miniaturize the lateral dimensions of structures within a plane. Such a multi-level metallization scheme requires level-penetrating contacts that are high-speed conductors and have good electromigration resistance and stress migration resistance.
The filling of a channel, via, or trench is made more difficult when the channel, via, or trench has a high aspect ratio, where aspect ratio is defined as height of the channel, via, or trench divided by the width thereof.
FIG. 1 depicts a semiconductor substrate 10 and a recess 12. Recess 12 can be a channel, via, or trench. In FIG. 2, a barrier layer 14 has been deposited within recess 12. For filling recess 12, a layer of aluminum or aluminum alloy 16 is deposited by physical or chemical vapor deposition, respectively, PVD and CVD. The CVD and PVD processes are typically conducted at a pressure of about 3 mTorr.
Barrier layer 14 is present to prevent the interdiffusion of silicon in semiconductor substrate 10 with the aluminum or aluminum alloy layer 16. Preferably, diffusion barrier 14 is formed of titanium nitride or titanium/tungsten, and is preferably situated between semiconductor substrate 10 and aluminum or aluminum alloy layer 16. A titanium nitride film is preferable in that it can promote the preferential development of a (111)-texture in an aluminum film that is subsequently deposited, which increases its physical stress and electromigration resistance. In addition to serving as a barrier material, titanium nitride films can also serve as an adhesive between semiconductor substrate 10 and aluminum or aluminum alloy layer 16.
FIG. 3 illustrates how aluminum or aluminum alloy layer 16 produced in this manner has poor step coverage for a high aspect ratio structure. Poor step coverage in a high aspect ratio structure is evinced by the xe2x80x9cbreadloafingxe2x80x9d effect that is seen in FIG. 3, where an overhang partially obscures the opening to recess 12 so as to cause a void therein. The presence of a void in recess 12, seen in FIGS. 3 and 4, detrimentally effects conductivity of aluminum or aluminum alloy layer 16. Improved step coverage of aluminum or aluminum alloy layer 16 within recess 12 is therefore desirable for reasons of electrical reliability. Additionally, improved metal flow and rapid elimination of voids with recess 12 without a weakening of barrier layer 14 is also desirable.
Due to the problem of poor or marginal step coverage in recess 12 and the creation of a void therein, aluminum or aluminum alloy layer 16 must be subjected to further treatment, for example by flowing of aluminum or aluminum alloy layer 16 by a heat treatment of brief duration such as rapid thermal processing (RTP), in combination with high pressure. If further structures are to be deposited on aluminum or aluminum alloy layer 16, then a height difference may result which must be compensated with a subsequently applied, non-conductive layer. A further difficulty arises when aluminum or aluminum alloy layer 16 is exposed to air. This exposure leads to the creation of a passivating layer containing aluminum oxide, which makes aluminum or aluminum alloy layer 16 less likely to flow adequately.
The prior art process to eliminate a void in a recess 12 using a combination of high pressure and high temperature creates a problem in that it may leave the barrier layer in a compromised state, as seen in FIG. 5. The deposition of aluminum or aluminum alloy layer 16 is typically at a pressure of about 3 mTorr, such that a void left in recess 12 has a pressure of about 3 mTorr which will typically collapse under typical RTP temperatures at a pressure of about 700 atmospheres. The atmosphere in which the high pressure is supplied is selected from a group of fluids that are inert to the device being built but have elemental or molecular diameters that will not penetrate the upper surface of the metallization layer which is seen in FIG. 3 as aluminum or aluminum alloy layer 16.
FIG. 5A depicts an enlarged view of FIG. 5, and particularly a region 20 which illustrates a potential result of the prior art process. The prior art high temperature RTP method described above tends to weaken barrier layer 14 so as to cause a breach 30 therein. Breach 30 permits the silicon of semiconductor substrate 10 to dissolve with aluminum or aluminum alloy layer 16.
RTP treatment, when used to eliminate a void in recess 12, tends to disrupt the crystallography of the titanium nitride film of barrier layer 14 as well as the preferential development of a (111)-texture in aluminum or aluminum alloy layer 16 that is subsequently deposited. While temperatures in excess of 450xc2x0 C. are required to initiate flowability of aluminum, a weakening of barrier layer 14 occurs above 450xc2x0 C. The melting point of aluminum begins to be evidenced at about 660xc2x0 C. With the weakening of barrier layer 14, the problem of junction spiking occurs if aluminum or aluminum alloy layer 16 becomes connected to a semiconductor substrate that contains silicon or polysilicon. Because of the solubility of silicon in aluminum, silicon diffuses into the aluminum conductor and precipitates out again at a later time. As a result, electrical leakage occurs from barrier layer 14 at breach 30. FIG. 5A depicts breach 30 where continued dissolution of silicon into the aluminum has created an enlargement of beach 30 at the base of the void within recess 12. Eventually, continued electrical leakage and the growing of the pit at the base of the void within recess 12 will destroy an electrical contact thereat and an a device associated therewith will fail. Electrical leakage alone will cause pure aluminum to electromigrate and, over time, an aluminum metal line will tend to thin out and become discontinuous due to electron crowding.
The present invention is drawn to a method of filling up a recess in a semiconductor substrate. Example of such as a recess are a channel, via, or trench. The filling of the recess eliminate voids therein. In the method, a barrier layer is formed within the recess. A first metal layer having a first melting point is then formed upon the barrier layer. The semiconductor substrate is then exposed to a selected pressure and a selected temperature sufficient to fill up the recess with the first metal layer. A second metal layer is formed upon the first metal layer, where the second metal layer has a melting point that is greater than that of the first metal layer. Preferably, the second metal layer has a melting point that is at least 10xc2x0 C. greater than that of the first metal layer, and most preferably at least 25xc2x0 C. greater.
In an alternative embodiment, there is deposited in the channel, via, or trench a barrier layer. Then, at least two aluminum alloy layers are deposited on the barrier layer. The at least two aluminum alloy layers may also be heat and pressure conditioned after deposition of the same. In so doing, the semiconductor structure and barrier layer, each of which underlies the channel, via, or trench, are not damaged. Preferably, the barrier layer is substantially composed of titanium nitride. A layer titanium may be deposited in the channel, via, or trench prior to the barrier layer.